Field of the Invention
This technology relates to a page buffer of a memory array.
Description of Related Art
Higher data densities result from the increasing number of bits per cell that can be stored on a nonvolatile memory array. However, an increased number of bits per cell carries the drawback of an increased delay during program and program verify steps.
A 1 bit per cell SLC (single level cell) stores 1 of 2 logical levels per cell, such that only one program level and program verify level exists. More bits per cell correspond to more program levels and program verify levels. For example, a 2 bits per cell MLC (multi level cell) stores 1 of 4 logical levels per cell; a 3 bits per cell TLC (triple level cell) stores 1 of 8 logical levels per cell; and a 4 bits per cell or 4LC (four level cell) stores 1 of 16 logical levels per cell. In contrast with SLC memory, memory cells that store multiple bits per cell have more than a single program level; multiple program levels and program verify levels exist.
The duration of a program step and a program verify step increases with the number of logical levels per cell. So as the number of bits per cell increase, the program step and the program verify step take longer. Similar difficulties exist with memory cells that store charge in different localized portions of the same memory cell.
It would be desirable to take advantage of the increased memory density of memory cells that store multiple bits per cell, without suffering a correspondingly increased duration of the program step and program verify step.